1. Field of the Invention
The present invention relates to an apparatus and method for analyzing C-V (Capacitance-Voltage) characteristics of a MIS (Metal/Insulator/Semiconductor) structure, and more particularly to an apparatus and method capable of analyzing C-V characteristics of a MIS structure which includes a thin silicon oxide film having a thickness of less than 3 nm.
2. Description of the Related Art
It is time consuming and troublesome to practically produce a transistor for the purpose of analyzing a gate insulator of the transistor. Accordingly, it would be advantageous if transistor characteristics, such as a drive current value, can be presumed without producing a transistor so as to determine these characteristics. A known method for presuming transistor characteristics without producing a transistor is to produce a MIS (Metal/Insulator/Semiconductor) structure and analyze C-V (Capacitance-Voltage) characteristics thereof by directly measuring capacitance of the MIS structure.
In recent years, dual gate (P+ gate and N+ gate) structures are coming into use as transistor gates. In a transistor having a dual gate structure, a boron ion injected into a P+ gate electrode is diffused to a channel section by heat treatment performed in a subsequent process, so that a threshold voltage of the transistor is changed.
FIG. 6 is a graph illustrating punch-through of a boron ion in a P+ gate electrode caused by heat treatment after the formation of a MIS structure. In the example shown in FIG. 6, a P-type MIS structure having a size of 9×10−4 cm2 is formed and its C-V characteristics are analyzed at various heat treatment temperatures. From FIG. 6, it is appreciated that at 1010° C. and 1020° C., respective C-V curves overlap each other and punch-through of a boron ion does not occur, and thus heat treatment at 1010° C. and 1020° C. is preferable. It is also appreciated that at 1050° C., the C-V curve is shifted to a positive potential side, which indicates that a boron ion is diffused to the substrate, and thus heat treatment at 1050° C. is not preferable. If the data shown in FIG. 6 is obtained before the production of the transistor, a transistor production process can be designed such that a heat treatment is performed at 1020° C. or lower. The measurement of C-V characteristics is becoming more important as a simple and efficient technique for analyzing whether or not punch-through of a boron ion occurs at a P+ gate electrode.
A known method for analyzing capacitance of an insulator is to experimentally form a MIS structure on a silicon substrate (a wafer or chip) as a test element group (TEG) and analyze C-V characteristics of the MIS structure using a measuring device (an LCR meter).
As LSI circuits are highly integrated, and by a demand for speedup of devices, the size of a device such as a transistor is becoming very small not only in its area but also in its thickness. In particular, a gate silicon oxide film is required to be 3 nm or lower in thickness. The C-V characteristics of such a very thin insulator cannot be accurately analyzed using conventional measuring devices in which unknown capacitance is directly measured.
FIG. 7 is a graph illustrating I-V characteristics of an N-type MOS (Metal/Oxide/Semiconductor) structure which includes as an insulator a silicon oxide film having a thickness of between about 1.5 nm and about 3.2 nm. As can be seen from FIG. 7, in the case of using such a silicon oxide film, when the thickness is 3 nm or more, F-N tunnel leakage current is dominant, and thus leakage current is very small. When the thickness is less than 3 nm, direct tunnel leakage current is dominant and leakage current is very large.
FIG. 8 is a graph illustrating C-V characteristics of an N-type MOS structure analyzed using a conventional C-V measuring device. As can be seen from FIG. 8, when an insulator has a thickness of about 3.2 nm, a measured C-V curve 71 indicates normal characteristics, but when the insulator has a thickness of about 2 nm, a measured C-V curve 73 deviates from an ideal curve 72 at a voltage of −1.5 V or lower. This is caused by the direct tunnel leakage current flowing through the insulator.
In a device including an extremely thin insulator, the speedup of the device can be achieved. However, an increase in leakage current causes problems. Thus, the thickness of the insulator is selected according to the purposes of the device. In other words, when it is desirable to decrease any consumption current by reducing leakage current, the device having a very thin insulator is not used. When the requirement for speedup of the device exceeds decrease in power consumption (current), a device having an insulator which is thinner than about 3 nm is used.
Another known method for analyzing capacitance of an insulator uses a non-contact-type C-V measuring device disclosed in Japanese Laid-Open Publication No. 6-112289.
FIG. 9 is an equivalent circuit diagram for schematically explaining insulator capacitance measured using the non-contact-type C-V measuring device disclosed in Japanese Laid-Open Publication No. 6-112289. In FIG. 9, Φms is a difference in work function of electrodes of the measuring device; Cair is spatial (air-gap) capacitance; Cox is insulator capacitance; and Cd is depletion-layer capacitance. Cair refers to capacitance in a space between an electrode provided in the measuring device and an insulator. By providing the electrode in the measuring device and the space between the electrode and the insulator, capacitance of the insulator can be measured immediately after the formation of the insulator without forming a MIS structure. Moreover, by providing a silicon wafer and the electrode which are out of contact with each other, the silicon wafer does not suffer contamination from the metal electrode. Thus, a subsequent step can be uninterruptedly performed on the silicon wafer after the capacitance measurement.
When the insulator capacitance is measured using the conventional measuring device illustrated in FIG. 9, it is required to accurately calculate capacitance in the space between the electrode and the insulator. In order to accurately calculate the capacitance in the space between the electrode and the insulator when the insulator has a thickness of 3 nm or less, it is required to precisely control the distances between the electrode and the insulator on the order of 0.01 nm. However, it is presently physically impossible to perform control on such an order. There arises an error in the capacitance in space between the electrode and the insulator. The difference prevents the accurate recognition of the insulator capacitance. Moreover, in the conventional technique, the distances between the electrode and the insulator are limited by dust existing in the measuring process. This is because the measuring device is damaged when dust causes a short circuit between the electrode and the insulator. It is difficult to place the electrode and the insulator as close to each other as a distance of 100 nm or less. Moreover, in the conventional technique, the capacitance measurement can only be performed immediately after the formation of the insulator, and it is impossible to perform the capacitance measurement after the formation of the electrode. Accordingly, it is impossible to analyze the boron ion punching-through from the P+ gate electrode as shown in FIG. 6.